Field of the Invention
The invention relates to a circuit configuration for producing negative voltages, including a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection, a second transistor having a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor, and a second capacitor having a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection, the transistors being MOS transistors produced in at least one triple well.
Such a circuit configuration is known from German Patent DE 196 01 369 C1. In that publication, the transistors are implemented as n-channel transistors in a p-well. The p-well is in turn produced in a deep, insulating n-well which is disposed in a p-substrate.
In principle, the circuit configuration can also be implemented in that way by using p-MOS transistors in an n-substrate.
The deep n-well is connected to ground potential, like the p-substrate. If the p-well is then given a more negative bias than the most negative voltage either at the drain connection or at the source connection of the first transistor, then no leakage current can flow when the circuit is in the steady state, not even through the parasitic well-substrate bipolar transistors. Thus, for example, an npn transistor is formed by the n.sup.+ -drain region which acts as an emitter of the NMOS transistor, the p-well which forms the base, and the n-well which forms the collector. When the well potential is more positive than the drain region of the NMOS transistor, the parasitic npn transistor will be switched on and will impair the efficiency of the charge pump.
The principle of the known circuit configuration operating as a charge pump is based on the fact that charges from a capacitor which is connected to the drain connection of the first transistor are "pumped" to a capacitor which is connected to the source connection of that transistor, by a voltage being alternately applied to the respective other capacitor connections. When a number N of circuit configurations of that type are connected in series, and the input of the first circuit configuration and the other connection of the capacitor connected to the output are connected to the ground connection, an output voltage of .vertline.(N-1)U.sub.O .vertline. can theoretically be obtained, where U.sub.O is the voltage at the clock signal connections.
The charging process is a dynamic process in which the voltages at the source and drain connections of the first transistors of the circuit configuration are constantly changing, with the result that the parasitic bipolar transistor is regularly switched on.
In order to solve that problem, German Patent DE 196 01 369 C1 proposes connecting the wells in which the transistors are disposed to the respective source connections of the transistors since, in the steady state, the most negative voltage in each case is present there. However, that assumption is in fact only true for the steady final state of the charge pump circuit, which will never actually occur in practice since the charge pump is continually discharged by a load.
As soon as the known circuit is switched on the well will be at a potential which corresponds to the clock signal voltage and is higher than the drain connection, and the bipolar transistor will therefore switch on. The result will be a massive efficiency loss since the charge pump firstly does not achieve the theoretically possible maximum output voltage and secondly adopts the output voltage to be reached much more slowly.